Preface Glossary Abbreviations 1 Digital to Analog conversion concepts 1.1 Functional aspects 1.1.1 Definition of the D／A function 1.1.2 Functional specifications 1.2 Algorithmic aspects 1.3 Signal processing aspects 1.3.1 Waveforms and Line coding 1.3.2 Signal Modulation concepts 1.4 Circuit aspects 1.4.1 Architecture terminology 1.4.2 Resistive Voltage division architectures 1.4.3 Capacitive Voltage and charge division architectures 1.4.4 Current division based architectures 1.5 Conclusions 1.5 Conclusions 2 Framework for Analysis and Synthesis of DACs 2.1 Overview 2.2 Framework description 2.2.1 Analysis 2.2.2 Synthesis 3 Current Steering DACs 3.1 Basic circuit 3.1.1 Partitioning and segmentation 3.1.2 Current switching network and current sources 3.1.3 Clock-data synchronization circuit 3.1.4 Auxiliary circuits 3.2 Implementations and technology impact 4 Dynamic limitations of Current Steering DACs 4.1 State of the art in dynamic linearity 4.2 Dynamic limitations of current steering DACs 4.2.1 Matching and relative amplitude precision 4.2.2 Matching and relative timing precision 4.3 Conclusions 5 Current Steering DAC circuit error analysis 5.1 Amplitude domain errors 5.1.1 Relative amplitude inaccuracies 5.1.2 Output resistance modulation 5.2 Time domain errors 5.2.1 Nonlinear settling and output impedance modulation 5.2.2 Asymmetrical switching 5.2.3 Modulation of switching behavior 5.2.4 Charge feedthrough and injection 5.2.5 Relative timing inaccuracies 5.2.6 Power supply bounce and substrate noise 5.2.7 Clock (timing) jitter 5.3 Conclusions 6 High-level modeling of Current Steering OACs 6.1 System modeling 6.1.1 System layers 6.1.2 System excitations and responses 6.1.3 System parameters 6.1.4 Subsystem interaction 6.1.5 System modulation 6.2 Error properties and classification 6.2.1 Error properties 6.2.2 Error classification 6.3 Functional error generation mechanisms 6.3.1 Definitions 6.3.2 Algorithmic modeling 6.3.3 Functional modeling 6.3.4 Examples 6.4 Conclusions 7 Functional modeling of timing errors 7.1 Non-uniform timing 7.1.1 The Equivalent Timing error of a transition 7.1.2 Non-uniform timing in the process of signal sampling 7.1.3 Non-uniform timing in the process of signal creation 7.2 Stochastic non-uniform timing analysis 7.2.1 Correlated non-uniform timing 7.2.2 White non-uniform timing 7.2.3 RZ and NRZ waveforms 7.3 Deterministic non-uniform timing 7.3.1 Non-linear mapping of time domains 7.3.2 Non-uniform timing in signal creation 7.4 Conclusions 8 Functional analysis of local timing errors 8.1 Local timing error analysis 8.1.1 Equivalent timing error calculation 8.1.2 Signal error calculation 8.2 High level architectural parameter tradeoffs: segmentation 8.3 Conclusions 9 Circuit analysis of local timing errors 9.1 Circuit analysis with linear models 9.1.1 Circuit behavioral-level analysis of timing errors in a chain 9.1.2 Transistor level analysis 9.2 Local timing error tradeoffs 9.2.1 Switch timing errors 9.2.2 Latch timing errors 9.3 Conclusions 10 Synthesis concepts for CS DACs 10.1 Information management in the CS DAC 10.1.1 The basic current steering DAC hardware 10.1.2 Information sources 10.1.3 Optional hardware" detection and control operations 10.1.4 Algorithms 10.1.5 Space/Time error mapping and processing 10.2 Synthesis Policy 10.3 A-posteriori error correction methods 10.3.1 Calibration in amplitude and time domain 10.3.2 Generalized mapping 10.3.3 Applications of generalized mapping 10.3.4 Realization issues of the generalized mapping concept 10.4 Conclusions 11 Design of a 12 bit 500 Msample/s DAC 11.1 Design approach 11.2 Architecturc 11.2.1 Signaling and circuit logic 11.2.2 Power supply and biasing 11.2.3 Thermometer/binary bits partitioning 11.3 Switched-Current cell 11.3.1 Current source 11.3.2 Switch 11.4 Decoder, data synchronization and conditioning 11.4.1 Binary-to-Thermometer decoder 11.4.2 Delay equalization 11.4.3 Master-slave latches and drivers 11.4.4 Clock buffer 11.5 Layout 11.6 Experimental results 11.6.1 DC linearity measurements 11.6.2 AC linearity measurements 11.7 Conclusions References Output spectrum for timing errors A.1 Power spectrum of y(t) for random timing errors A.2 Spectrum of y(t) for deterministic timing errors B Literature data
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